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| BACK LR38666Y LR38666Y DESCRIPTION The LR38666Y is a CMOS digital signal processor for color digital still camera systems of 1 310 k/ 2 140 k/ 3 300 k/3 370 k/4 200 k-pixel CCDs with primary color mosaic filters. One-chip System LSI for Digital Still Cameras * Power supplies - +2.5 V for digital/analog circuits - +3.3 V for digital circuits * Package : 240-ball CSP (T-TFBGA240-1414) FEATURES * ARM7TDMI is used as the CPU core * CCD signal processor modules - Supported image size : 1 310 k/ 2 140 k/3 300 k/ 3 370 k/4 200 k pixels - R, G and B primary color mosaic filters : Bayer matrix, 10 bits per color - Built-in auto focus, auto exposure and auto white balance functions - Built-in digital clamp and gamma correction functions * Video encoder module - Composite analog signal output mode : Switchable between NTSC and PAL - Built-in OSDC function * JPEG encoding/decoding module : Built-in circuits for encoding and decoding - Encoding rate : Max. 66 ms per frame (for 1/10-compression in VGA mode) - Decoding rate : Max. 66 ms per frame (for decompression in VGA mode) (Assuming that SDRAM is used and the internal bus is occupied by the JPEG module) * SDRAM/flash memory controller module * Synchronous/asynchronous SIO * USB 1.0 is supported * General purpose I/O ports * Built-in audio I/F * Built-in resizing function * Built-in CompactFlash I/F * Built-in SmartMedia I/F In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LR38666Y PIN CONNECTIONS 240-BALL CSP TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Index mark A NC 237 PLVDD 236 238 239 DGND 232 234 DVDD 228 230 C29MI 227 SDI0 221 C24MI 215 ASCLK 209 TGED1 204 CCDIN6 198 COMI 193 DVDD2 188 TGID 186 DIREF2 183 DAVDD NC PLGND TESTCLK2 DVDD2 B C D E F G H J K L M N P R T 3 6 8 13 DVDD2 1 2 5 9 DGND 224 DVDD 218 DVDD 212 ASDO 206 CCDIN8 201 DVDD 195 CCDIN1 190 TGCLK 185 DVREF2 182 178 DIREF1 181 179 DVREF1 177 VB1 MEMCKE3 MEMCKE1 PLGND DAGND YCOUT 235 PLVDD 231 SDO0 225 SCLK0 219 SDI1 213 TCLK 207 208 TGED0 200 202 CCDIN4 194 192 VD 189 DVDD 184 COUT 176 DGND MEMCS2Z MEMCKE2 CCDIN9 CCDIN3 CCDIN0 4 7 DVDD 233 10 MEMD0 229 11 MEMD1 226 DGND 220 DGND 211 ASDI 187 VB2 173 GIO14 175 RESETZ 174 GIO15 172 GIO13 MEMCS3Z MEMCS1Z MEMCS0Z ICEFIQZ C29MO 223 222 22 MEMD8 217 216 210 214 205 CCDIN7 199 DGND 196 CCDIN2 191 HD 169 GIO11 171 164 DGND 170 165 GIO7 168 166 GIO8 SDO1 ARSYNCO TGED2 GIO12 TESTCLK GIO10 19 DVDD 14 MEMD3 15 DGND 12 MEMD2 16 MEMD4 203 CCDIN5 197 COMO 162 GIO5 163 GIO6 167 GIO9 C24MO AXSYNCO DGND 25 29 DVDD 20 27 MEMD12 21 DGND 18 MEMD6 17 MEMD5 156 GIO1 157 GIO2 161 GIO4 159 GIO3 158 DVDD2 160 DVDD MEMD11 MEMD7 26 DGND 24 31 37 48 DGND 23 30 40 DGND 28 34 36 TST3Z 150 CFA1 151 CFA2 155 GIO0 153 DGND 152 CFA3 154 CFA4 MEMD10 MEMD9 MEMD13 35 41 45 MEMD21 32 38 44 DVDD 33 DGND 143 CFD11 145 CFD13 148 CFD15 147 CFD14 146 DVDD 149 CFA0 TEST2Z TEST1Z MEMD15 MEMD14 MEMD16 39 46 MEMD22 137 CFD8 139 DVDD2 142 TEST7Z 141 DGND 140 CFD10 144 CFD12 MEMD20 MEMD18 MEMD19 MEMD17 43 71 70 67 69 DVDD2 42 76 MEMA3 82 77 MEMA4 89 DGND 94 DVDD2 96 100 97 99 MEMA18 102 107 103 106 DGND 133 DGND 136 CFD7 134 CFD5 135 CFD6 138 CFD9 TEST5Z TEST4Z TEST6Z MEMA16 MEMA20 47 MEMD23 50 DVDD2 51 55 58 62 66 49 53 64 65 68 83 85 DGND 90 91 93 DGND 131 109 111 110 108 130 CFD2 127 CFD0 129 DVDD 132 CFD4 MEMD25 MEMD24 MEMA0 MEMA8 MEMA12 DGND FL_EXWEZ CFD3 52 MEMD26 54 DGND 72 73 DGND 79 DGND 113 115 114 112 DVDD 124 118 119 116 125 122 121 117 128 CFD1 MEMD28 MEMD27 MEMWEZ MEMA1 MEMA13 MEMA17 FLCE0Z FLRP0Z EXCS1Z CFRST CFCE1Z 56 DVDD 59 61 63 80 81 MEMA7 87 86 DVDD 126 123 DGND MEMD31 MEMD30 MEMRASZ DGND MEMA6 MEMA10 EXCS0Z EXDACK1Z CFCD1Z CFREGZ CFCE2Z 57 MEMD29 75 DVDD 92 MEMA14 98 DVDD 104 105 DGND MEMLDQM MEMCASZ FLCE1Z FLRP1Z EXDACK0Z CFCD2Z CFWAITZ 74 78 MEMA5 84 88 95 101 NC MEMUDQM DVDD MEMCLK MEMA2 MEMA9 MEMA11 MEMA15 MEMA19 FL_EXOEZ FLWPZ EXINTZ CFRDBY NC (T-TFBGA240-1414) 2 LR38666Y BLOCK DIAGRAM CCDIN0CCDIN9 GIO0-GIO15 (NOTE 4) TGID TGCLK TGED0TGED2 HD VD CCD SIGNAL PROCESSOR 1 GIO USB YCOUT COUT DVREF1, DVREF2 DIREF1, DIREF2 VB1, VB2 COMI COMO C24MI C24MO C29MI C29MO ASDI ASDO ASCLK AXSYNCO ARSYNCO TESTCLK TESTCLK2 TCLK TEST1ZTEST7Z CLOCK GENERATOR CCD SIGNAL PROCESSOR 2 D/A CONVERTER PLL AUDIO I/F JPEG COMPRESSOR/ DECOMPRESSOR NTSC/PAL ENCODER RESIZE TIMER SDI0 SDO0 SCLK0 SDI1 SDO1 USART DMAC UART LOCAL SRAM 4 K BYTES CPU PERIPHERAL DECODER RESETZ ICEFIQZ CFA0-CFA4 CFD0-CFD15 (NOTE 5) ARM7TDMI BUS CONTROLLER MEMORY CONTROLLER (NOTE 1) (NOTE 2) MEMD0MEMD31 MEMA0MEMA20 CONTROL SIGNAL CONTROL SIGNAL NOTES : 1. Control signal for SDRAM MEMCLK, MEMLDQM, MEMUDQM, MEMWEZ, MEMCASZ, MEMRASZ, MEMCKE1, MEMCS0ZMEMCS3Z Control signal for SDRAM or general purpose I/O. MEMCKE2 = GIO16, MEMCKE3 = GIO17 (set by register) 2. Control signal for flash memory and external device. FLCE0Z, FL_EXOEZ, FL_EXWEZ, FLWPZ, FLRP0Z, EXCS0Z, CFREGZ, CFRST, CFCE1Z to CFCE2Z Control signal for flash memory and external device or general purpose I/O FLCE1Z = GIO18, FLRP1Z = GIO19, EXCS1Z = GIO20 (set by register) 3. Input signal from external device EXDACK0Z, EXINTZ, CFWAITZ, CFRDBY Input signal from external device or general purpose I/O. EXDACK1Z = GIO21, CFCD1Z = GIO22, CFCD2Z = GIO23 (set by register) 4. General purpose I/O or PWM. GIO0 to GIO2 = CCDGEO0 to CCDGEO2, GIO9 = TX_VPO, GIO10 = TX_VMO, GIO11 = TX_OE_N, GIO12 = SUSPEND_N, GIO13 = RX_VPI, GIO14 = RX_VMI, GIO15 = RX_DATA (set by register) 5. Data I/O for CompactFlash or general purpose I/O. CFD8 = GIO24, CFD9 = GIO25, CFD10 = GIO26, CFD11 = GIO27, CFD12 = GIO28, CFD13 = GIO29, CFD14 = GIO30, CFD15 = GIO31 (set by register) 3 CONTROL SIGNAL (NOTE 3) LR38666Y PIN DESCRIPTION PIN NO. COORDINATE SYMBOL 1 2B MEMCKE1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 2C 1B 3D 2D 1C 3E 1D 2E 4E 5E 4F 1E 2F 3F 5F 5G 4G 1F 2G 3G 6G 5H 4H 1G 3H 2H 6H 1H 5J 4J 2J 3J 6J 1J 6K 4K 2K 3K MEMCKE2 MEMCKE3 MEMCS0Z MEMCS1Z MEMCS2Z DVDD MEMCS3Z DGND MEMD0 MEMD1 MEMD2 DVDD2 MEMD3 DGND MEMD4 MEMD5 MEMD6 DVDD MEMD7 DGND MEMD8 MEMD9 MEMD10 MEMD11 DGND MEMD12 MEMD13 DVDD MEMD14 MEMD15 TEST1Z DGND MEMD16 TEST2Z TEST3Z MEMD17 MEMD18 MEMD19 IO SYMBOL DESCRIPTION IO8 SDRAM clock enable, Block 1 IO8 IO8 IO8 IO8 IO8 - IO8 - IO12U IO12U IO12U - IO12U - IO12U IO12U IO12U - IO12U - IO12U IO12U IO12U IO12U - IO12U IO12U - IO12U IO12U IU - IO12U IU IU IO12U IO12U IO12U Data I/O for SDRAM/flash memory/external device Power supply (+3.3 V) Data I/O for SDRAM/flash memory/external device Ground SDRAM clock enable, Block 2/GIO16 SDRAM clock enable, Block 3/GIO17 SDRAM chip select, Block 0 SDRAM chip select, Block 1 16-bit data mode : SDRAM chip select, Block 2 32-bit data mode : Control MEMD15 to MEMD8 of SDRAM Power supply (+3.3 V) 16-bit data mode : SDRAM chip select, Block 3 32-bit data mode : Control MEMD7 to MEMD0 of SDRAM Ground Data I/O for SDRAM/flash memory/external device Internal power supply (+2.5 V) Data I/O for SDRAM/flash memory/external device Ground Data I/O for SDRAM/flash memory/external device Ground Data I/O for SDRAM/flash memory/external device Power supply (+3.3 V) Data I/O for SDRAM/flash memory/external device Test (Must be open.) Ground Data I/O for SDRAM/external device/GIO16 Test (Must be open.) Data I/O for SDRAM/external device/GIO17 Data I/O for SDRAM/external device/GIO18 Data I/O for SDRAM/external device/GIO19 4 LR38666Y PIN NO. COORDINATE SYMBOL 40 5K DGND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 1K 6L 5L 2L 1L 3L 1M 4L 4M 2M 3M 1N 4N 2N 3N 1P 1R 3P 2P - 2R 3R 2T 4P 4R 3T 5P 4T 5R 5N 5M 6N 6P 5T 6R 6M 7M 6T 7N MEMD20 TEST4Z TEST5Z DVDD MEMD21 MEMD22 MEMD23 DGND MEMD24 DVDD2 MEMD25 MEMD26 MEMD27 DGND MEMD28 DVDD MEMD29 MEMD30 MEMD31 NC DGND MEMLDQM MEMUDQM MEMRASZ MEMCASZ DVDD DGND MEMCLK DVDD2 MEMWEZ MEMA0 MEMA1 DGND MEMA2 DVDD MEMA3 MEMA4 MEMA5 DGND IO SYMBOL - Ground IO12U IU IU - IO12U IO12U IO12U - IO12U - IO12U IO12U IO12U - IO12U - IO12U IO12U IO12U - - O12 O12 O12 O12 - - IO12 - O12 O12 O12 - O12 - O12 O12 O12 - DESCRIPTION Data I/O for SDRAM/external device/GIO20 Test (Must be open.) Power supply (+3.3 V) Data I/O for SDRAM/external device/GIO21 Data I/O for SDRAM/external device/GIO22 Data I/O for SDRAM/external device/GIO23 Ground Data I/O for SDRAM/external device/GIO24 Internal power supply (+2.5 V) Data I/O for SDRAM/external device/GIO25 Data I/O for SDRAM/external device/GIO26 Data I/O for SDRAM/external device/GIO27 Ground Data I/O for SDRAM/external device/GIO28 Power supply (+3.3 V) Data I/O for SDRAM/external device/GIO29 Data I/O for SDRAM/external device/GIO30 Data I/O for SDRAM/external device/GIO31 Must be open. Ground 16-bit data mode : Control MEMD7-MEMD0 of SDRAM 32-bit data mode : Control MEMD23-MEMD16 of SDRAM 16-bit data mode : Control MEMD15-MEMD8 of SDRAM 32-bit data mode : Control MEMD31-MEMD24 of SDRAM SDRAM row address strobe SDRAM column address strobe Power supply (+3.3 V) Ground SDRAM clock output (49.0908 MHz : double of C24MI input) Internal power supply (+2.5 V) SDRAM write enable Address for SDRAM/flash memory/external device Ground Address for SDRAM/flash memory/external device Power supply (+3.3 V) Address for SDRAM/flash memory/external device Address for SDRAM/flash memory/external device Address for SDRAM/flash memory/external device Ground 5 LR38666Y PIN NO. COORDINATE SYMBOL 80 7P MEMA6 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 7R 7L 8M 7T 8N 8R 8P 8T 8L 9M 9N 9R 9P 9L 9T 10L 10N 10R 10P 10M 10T 11L 11N 11R 11T 11P 11M 12T 12N 12R 12P 13T 13N 13R 13P 14T 15T 14P 14R - MEMA7 TEST6Z MEMA8 MEMA9 DGND DVDD MEMA10 MEMA11 DGND MEMA12 MEMA13 MEMA14 DGND DVDD2 MEMA15 MEMA16 MEMA17 DVDD MEMA18 DGND MEMA19 MEMA20 FLCE0Z FLCE1Z FL_EXOEZ DGND FL_EXWEZ FLWPZ FLRP0Z FLRP1Z EXCS0Z DVDD EXCS1Z EXDACK0Z EXDACK1Z EXINTZ CFRDBY CFCD1Z CFCD2Z NC IO SYMBOL DESCRIPTION O12 Address for SDRAM/flash memory/external device O12 IU O12 O12 - - O12 O12 - O12 O12 O12 - - O12 O12 O12 - O12 - O12 O12 O8 IO8 O8 - O8 O8 O8 IO8 O8 - IO8 IU IO8U IU IU IO8U IO8U - Address for SDRAM/flash memory/external device Test (Must be open.) Address for SDRAM/flash memory/external device Address for SDRAM/flash memory/external device Ground Power supply (+3.3 V) Address for SDRAM/flash memory/external device Address for SDRAM/flash memory/external device Ground Address for SDRAM/flash memory/external device Address for SDRAM/flash memory/external device Address for SDRAM/flash memory/external device Ground Internal power supply (+2.5 V) Address for flash memory/external device/CompactFlash (CFA5) Address for flash memory/external device/CompactFlash (CFA6) Address for flash memory/external device/CompactFlash (CFA7) Power supply (+3.3 V) Address for flash memory/external device/CompactFlash (CFA8) Ground Address for flash memory/external device/CompactFlash (CFA9) Address for flash memory/external device/CompactFlash (CFA10) Chip enable for flash memory, Block 0 Chip enable for flash memory, Block 1/GIO18 Output enable for flash memory/external device/CompactFlash Ground Write enable for flash memory/external device/CompactFlash Write protect for flash memory Reset/deep power down for flash memory, Block 0 Reset/deep power down for flash memory, Block 1/GIO19 Chip select 0 for external device Power supply (+3.3 V) Chip select 1 for external device/GIO20 Data acknowledge 0 for external device Data acknowledge 1 for external device/GIO21 External device interrupt CompactFlash/SmartMedia READY/BUSY CompactFlash/SmartMedia card detect signal 1/GIO22 CompactFlash card detect signal 2/SmartMedia write protect detect/GIO23 Must be open. 6 LR38666Y PIN NO. COORDINATE SYMBOL 121 15R CFWAITZ 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 15P 16R 14N 15N 16P 14M 16N 15M 13M 12M 16M 12L 14L 15L 13L 11K 16L 12K 15K 14K 13K 11J 16K 12J 15J 14J 13J 16J 11H 12H 15H 14H 16H 13H 11G 12G 15G CFREGZ DGND CFRST CFCE1Z CFCE2Z CFD0 CFD1 DVDD CFD2 CFD3 CFD4 DGND CFD5 CFD6 CFD7 CFD8 CFD9 DVDD2 CFD10 DGND TEST7Z CFD11 CFD12 CFD13 DVDD CFD14 CFD15 CFA0 CFA1 CFA2 CFA3 DGND CFA4 GIO0 GIO1 GIO2 DVDD2 IO SYMBOL DESCRIPTION IU CompactFlash -WAIT signal IO8 - IO8 IO8 IO8 IO8U IO8U - IO8U IO8U IO8U - IO8U IO8U IO8U IO8U IO8U - IO8U - IU IO8U IO8U IO8U - IO8U IO8U IO8 IO8 IO8 IO8 - IO8 IO8 IO8 IO8 - Internal power supply (+2.5 V) Ground Data I/O for CompactFlash/SmartMedia Data I/O for CompactFlash/GIO24 Data I/O for CompactFlash/GIO25 Internal power supply (+2.5 V) Data I/O for CompactFlash/GIO26 Ground Test (Must be open.) Data I/O for CompactFlash/GIO27 Data I/O for CompactFlash/GIO28 Data I/O for CompactFlash/GIO29 Power supply (+3.3 V) Data I/O for CompactFlash/GIO30 Data I/O for CompactFlash/GIO31 Address for CompactFlash/read enable for SmartMedia (-RE) Address for CompactFlash/write enable for SmartMedia (-WE) Address for CompactFlash/write protect for SmartMedia (-WP) Address for CompactFlash/address latch enable for SmartMedia (ALE) Ground Address for CompactFlash/command latch enable for SmartMedia (CLE) General purpose I/O (+3.3 V)/PWM/CCD general purpose output CompactFlash -REG signal Ground CompactFlash reset signal (RESET)/SmartMedia chip enable (-CE) Card enable 1 for CompactFlash (-CE1) Card enable 2 for CompactFlash (-CE2) Data I/O for CompactFlash/SmartMedia Power supply (+3.3 V) Data I/O for CompactFlash/SmartMedia 7 LR38666Y PIN NO. COORDINATE SYMBOL 159 14G GIO3 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 16G 13G 11F 12F 14F 15F 16F 13F 16E 13E 15E 14E 16D 13D 15D 14D 16C 16B 14C 15C - 15B 14B 15A 13C 13B 14A 12D 13A 12C DVDD GIO4 GIO5 GIO6 DGND GIO7 GIO8 GIO9 GIO10 GIO11 TESTCLK GIO12 GIO13 GIO14 GIO15 RESETZ DGND VB1 DIREF1 DVREF1 NC YCOUT DAGND DAVDD COUT DVREF2 DIREF2 VB2 TGID DVDD IO SYMBOL DESCRIPTION IO8 General purpose I/O (+3.3 V)/PWM - IO8 IO8 IO8 - IO8 IO8 IO8 IO8 IO8 I IO8 IO8 IO8 IO8 IS - - DAIREF DAVREF - DAI - - DAI DAVREF DAIREF - I - General purpose I/O (+3.3 V)/PWM Ground General purpose I/O (+3.3 V)/PWM General purpose I/O (+3.3 V)/PWM/TX_VPO output for USB (send data +) General purpose I/O (+3.3 V)/PWM/TX_VMO output for USB (send data -) General purpose I/O (+3.3 V)/PWM/TX_OE_N output for USB (send enable) Ground General purpose I/O (+3.3 V)/PWM/SUSPEND_N output for USB (suspend request) General purpose I/O (+3.3 V)/PWM/RX_VPI input from USB (receive data +) General purpose I/O (+3.3 V)/PWM/RX_VMI input from USB (receive data -) General purpose I/O (+3.3 V)/PWM/RX_DATA input from USB (receive enable) Reset Ground Biased voltage output 1 DAC reference current output 1 DAC full scaled reference voltage input 1 Must be open. NTSC/PAL composite/luminance analog output (1 Vp-p : must be connected to 75 $.) Ground for DAC Power supply for DAC (+2.5 V) NTSC/PAL composite/chrominance analog output (1 Vp-p : must be connected to 75 $) DAC full-scale reference voltage input 2 DAC reference current output 2 Bias voltage output 2 Identification pulse for color line of CCD signal from TG (High at R-line) Power supply (+3.3 V) Power supply (+3.3 V) 8 LR38666Y PIN NO. COORDINATE SYMBOL 190 12B TGCLK 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 12E 11D 12A 11C 11B 11E 10F 11A 10E 10C 10B 10D 9F 10A 9E 9B 9C 9D 9A 8E 8D 8B 8C 8F 8A 7F 7E 7B 7C 7D 7A 6F 6E 6B 6C 6D 6A 5A 5D 5B HD VD DVDD2 CCDIN0 CCDIN1 CCDIN2 COMO COMI DGND CCDIN3 DVDD CCDIN4 CCDIN5 CCDIN6 CCDIN7 CCDIN8 CCDIN9 TGED0 TGED1 TGED2 ASDI ASDO TCLK DGND ASCLK AXSYNCO ARSYNCO DVDD SDI1 DGND C24MI C24MO SDO1 DVDD SCLK0 DGND SDI0 DVDD2 C29MO C29MI IO SYMBOL DESCRIPTION I Pixel clock input from TG IO8 IO8 - I I I OSC IA - I - I I I I I I IO8 IO8 O8 IU O8 I - O8 O8 O8 - I - IA OSC O8 - IO8U - I - OSC IA Serial signal output for setting register of TG Input data for audio serial I/F Output data for audio serial I/F Master clock input for audio serial I/F Ground Shift clock for audio serial I/F Transmit synchronous signal for audio serial I/F Receive synchronous signal for audio serial I/F Power supply (+3.3 V) Input data for asynchronous serial I/F Ground 24.5454 MHz crystal oscillator input (system clock) 24.5454 MHz crystal oscillator output Output data for asynchronous serial I/F Power supply (+3.3 V) Clock for synchronous serial I/F Ground Input data for synchronous serial I/F Internal power supply (+2.5 V) 29.5 MHz crystal oscillator output 29.5 MHz crystal oscillator input (for PAL) Horizontal synchronization pulse for CCD Vertical synchronization pulse for CCD Internal power supply (+2.5 V) RGB input from CCD 24 MHz crystal oscillator output 24 MHz crystal oscillator input (for communication) Ground RGB input from CCD Power supply (+3.3 V) RGB input from CCD 9 LR38666Y PIN NO. COORDINATE SYMBOL 231 5C SDO0 232 233 234 235 236 237 238 239 240 I IS IU O8 O12 IO8 IO8U : : : : : : : IO SYMBOL DESCRIPTION O8 Output data for synchronous serial I/F I IU - - - - - - - Input signal for test (Must be connected to ground.) FIQ interrupt input for ROMICE (Must be open during normal operation.) Power supply (+3.3 V) Power supply for PLL (+2.5 V) Ground for PLL Power supply for PLL (+2.5 V) Ground for PLL Ground Must be open. IO12 IO12U DAI DAVREF DAIREF IA OSC : : : : : : : Input/output pin Input/output pin with pull-up resistor Analog output pin Analog input pin for DAC Analog output pin for DAC Input pin for oscillation Output pin for oscillation 4A 4D 4B 4C 3A 2A 3B 3C - TESTCLK2 ICEFIQZ DVDD PLVDD PLGND PLVDD PLGND DGND NC Input pin Schmidt input pin Input pin with pull-up resistor Output pin Output pin Input/output pin Input/output pin with pull-up resistor REMARKS : PIN TYPE (MAX. OUTPUT CURRENT) +3.3 V I/O pin (12 mA) or output pin APPLICABLE PINS MEMLDQM, MEMUDQM, MEMCLK, MEMWEZ, MEMCASZ, MEMRASZ, MEMA0 to MEMA20 MEMCKE1 to MEMCKE3, MEMCS0Z to MEMCS3Z, FLCE0Z to FLCE1Z, FL_EXOEZ, FL_EXWEZ, FLWPZ, FLRP0Z to FLRP1Z, EXCS0Z to EXCS1Z, CFREGZ, CFRST, CFCE1Z to CFCE2Z, CFA0 to CFA4, GIO0 to GIO15, HD, VD, TGED0 to TGED2, ASDO, ASCLK, AXSYNCO, ARSYNCO, SDO1, SDO0 +3.3 V I/O pin (12 mA, 98 k$ pull-up MEMD0 to MEMD31 resistor installed) +3.3 V I/O pin (8 mA, 98 k$ pull-up resistor installed) or input pin TEST1Z to TEST7Z, EXDACK0Z to EXDACK1Z, EXINTZ, CFRDBY, CFWAITZ, CFD0 to CFD15, ASDI, SCLK0, ICEFIQZ +3.3 V I/O pin (8 mA) or output pin NOTES : 1. When an I/O pin is set to "input", take care not to let the pin to have a floating address. 2. Keep test pins TEST1Z to TEST7Z normally open. 3. I/O pins MEMCKE2, MEMCKE3, FLCE1Z, FLRP1Z, EXCS1Z and MEMCLK are set to "output" when reset (RESETZ input is Low level), while other I/O pins are "input". 10 LR38666Y FUNCTIONAL DESCRIPTION Oscillation Circuit The PLL included in the LR38666Y divides or passes through the doubled frequency of the quartz crystal connected to I/O pins, and provides it to the internal logic circuits as shown in Fig.1 and Fig.2. C24MI (or C29MI or COMI) Oscillation Circuit (PLL) Frequency Divider To Internal Logic C24MO (or C29MO or COMO) Fig. 1 Block Diagram of Oscillation Circuit C1 C24MI (or C29MI or COMI) RD2 C2 RD1 C24MO (or C29MO or COMO) Fig. 2 Clock Input to Oscillation Circuit Connection of Quartz Crystal (TA = 0 to +70C) : Example of Oscillation under Fundamental Frequencies APPLICABLE PINS C24MI, C24MO C29MI, C29MO COMI, COMO FUNDAMENTAL FREQUENCY [MHz] 24.5454 29.5000 24.0000 C1 [pF] 10 10 10 RECOMMENDED COEFFICIENT C2 [pF] RD1 [$] 10 220 10 10 220 220 RD2 [$] 1M 1M 1M NOTES : 1. The oscillation circuit should be located as close to C24MI, C24MO (C29MI, C29MO, COMI, COMO) as possible. 2. Do not install other signal lines in the shaded area. 3. Perform due evaluation on the match between the LR38666Y and the quartz crystal. 11 LR38666Y Clock The clock supplied to C24MI is doubled in frequency by an internal PLL and then is used as the main system clock. This clock is also used by the NTSC/PAL module in NTSC mode. The clock supplied to C29MI is doubled in frequency by an internal PLL and then is used by the NTSC/PAL module in PAL mode only. The PAL mode allows clock oscillation. If the PAL mode is not used, fix the input level to High or Low. Note that, in NTSC mode, the accuracy of burst signals (deflection from the specified frequency) for video output depends on the accuracy of the clock supplied to C24MI. In PAL mode, the accuracy of burst signals (deflection from the specified frequency) for video output depends on the accuracy of the clock supplied to C29MI. The clock supplied to COMI is doubled in frequency by an internal PLL and then is used by the UART, USART, USB and AUDIOIF modules. Only 24 MHz frequency can be used. Note that the accuracy of the clock supplied to COMI influences the pulse width of the I/O signals. Supply the clock (synchronized with CCD data) to TGCLK. Use as low a noise level signal as possible. Note that accuracy of the clock supplied to TCLK influences the accuracy of the clock of AUDIOIF. If TCLK is not used, fix the input level to High or Low. Power Supply Pins Connect low noise power lines to the PLL power supply pin (PLVDD), the PLL ground pin (PLGND), the DA converter power supply pin (DAVDD) and the DA converter ground pin (DAGND). Note that PLVDD and DAVDD are connected to DVDD2, and PLGND and DAGND are connected to DGND inside the LR38666Y. Power ON/OFF Sequence Two power supplies are used with the LR38666Y. One (DVDD) is used for I/O buffer and the other (DVDD2) is used for the core logic circuits. Power ON : Be sure to turn ON the internal power supply of DVDD2 first. Power OFF : Be sure to turn OFF the I/O buffer of DVDD first. Recommended DAC Circuit (Example) DAVDD DAVDD Analog Output DAVDD RB1 CVR RB2 VREF ROUT YCOUT/COUT DVREF1/2 RREF DIREF1/2 CVB VB1/2 DAGND 12 LR38666Y ABSOLUTE MAXIMUM RATINGS PARAMETER I/O power supply voltage Internal power supply voltage Input voltage Output voltage Storage temperature SYMBOL DVDD DVDD2 VI VO TSTG RATING -0.3 to +4.3 -0.3 to +3.3 -0.3 to DVDD + 0.3 -0.3 to DVDD + 0.3 -55 to +150 UNIT V V V V C RECOMMENDED OPERATING CONDITIONS PARAMETER Power supply voltage Operating temperature Operating frequency SYMBOL CONDITIONS I/O digital power supply DVDD DVDD2 Internal digital power supply DAVDD Analog power supply TOPR fOPR Maximum operating frequency MIN. 3.0 2.25 2.25 0 TYP. MAX. 3.3 3.6 2.5 2.75 2.5 2.75 +25 +70 49.0908 UNIT V V V C MHz 13 LR38666Y ELECTRICAL CHARACTERISTICS DC Characteristics PARAMETER Input "Low" voltage Input "High" voltage Positive trigger voltage Negative trigger voltage Hysteresis Input leakage current SYMBOL VIL VIH VT+ VT- VT+ - VT- VIN = 0 V to DVDD II VIN = DVDD [with pull-up 98 k$] VIN = 0 V [with pull-up 98 k$] IOL = 8 mA IOH = -8 mA IOL = 12 mA IOH = -12 mA VREF = 1.24 V RREF = 4.8 k$ ROUT = 75 $ CVB = 0.1 F 1.12 DVDD - 0.5 0.5 DVDD - 0.5 9 -3.0 -1.0 16.5 75 1.24 4.8 24.5454 29.5000 24.0000 Input image display mode : 1/4 VGA 55 115 70 125 25 15 1.36 +6.0 +1.0 0.2 -1.0 -5.0 -35 0.5 (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) CONDITIONS MIN. 0.8 DVDD 1.37 1.33 +1.0 +5.0 TYP. MAX. UNIT 0.2 DVDD V V V V V A A A V V V V Bit LSB LSB mA $ V k$ MHz MHz MHz mA 13 mA mA 14 mA mA 15 mA 8 9 10 11 12 7 2 3 4 4 5 6 NOTE 1 Input "Low" current Output "Low" voltage 1 Output "High" voltage 1 Output "Low" voltage 2 Output "High" voltage 2 Resolution Linearity error Differential linearity error Full-scale current Output load resistance Reference voltage Reference resistance Oscillation frequency 1 Oscillation frequency 2 Oscillation frequency 3 Supply current (a) (DVDD) Supply current (a) (DVDD2, DAVDD, PLVDD) Supply current (b) (DVDD) Supply current (b) (DVDD2, DAVDD, PLVDD) Standby current (DVDD) Standby current (DVDD2, DAVDD, PLVDD) IIL VOL1 VOH1 VOL2 VOH2 RES EL ED IFS ROUT VREF RREF FOSC1 FOSC2 FOSC3 IDDa IDD2a IDDb IDD2b IDDSB IDD2SB Input image display & capture image mode : VGA waiting for ARM operation with 1/4 clock 14 LR38666Y NOTES : 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Applicable to IO symbols I, IU, IO8, IO8U, IO12, IO12U. Applicable to IO symbol IS. Applicable to IO symbols I, IO8, IO12, IS. Applicable to IO symbols IU, IO8U, IO12U. Applicable to IO symbols O8, IO8, IO8U. Applicable to IO symbols O12, IO12, IO12U. Applicable to IO symbol DAI. Applicable to IO symbol DAVREF. External resistance value. Applicable to IO symbol DAIREF. Applicable to IO symbols IA (C24MI), OSC (C24MO). Applicable to IO symbols IA (C29MI), OSC (C29MO). Applicable to IO symbols IA (COMI), OSC (COMO). Supply voltage DVDD : 3.3 V, DVDD2 : 2.5 V Measuring conditions : 1 310 k-pixel CCD is used. CCD1 output image size 640 x 240, CCD2 output image size 320 x 240, 16 bits external bus width, Local SRAM is not used. Always active modules : ARM, CCD1, CCD2, VENC, MEMC, DMAC Inactive modules : JPEG, SRAM, USART, UART, USB, RESIZE, PLL (for PAL), AUDIOIF, GIO 14. Supply voltage DVDD : 3.3 V, DVDD2 : 2.5 V Measuring conditions : 1 310 k-pixel CCD is used. CCD1 output image size 640 x 480, CCD2 output image size 640 x 480, 16 bits external bus width, Local SRAM is not used. Always active modules : ARM, CCD1, CCD2, JPEG, VENC, MEMC, DMAC Inactive modules : SRAM, USART, UART, USB, RESIZE, PLL (for PAL), AUDIOIF, GIO 15. Supply voltage DVDD : 3.3 V, DVDD2 : 2.5 V Always active modules : ARM, MEMC, DMAC (Internal clock is divided into 1/4.) Inactive modules : JPEG, CCD1, CCD2, VENC, SRAM, USART, UART, USB, RESIZE, PLL (for PAL), AUDIOIF, GIO 15 LR38666Y AC Characteristics SDRAM INTERFACE TIMING TMCLK 0.8 DVDD MEMCLK 0.2 DVDD TMCLKL MEMCS0Z-MEMCS3Z MEMRASZ MEMCASZ MEMWEZ MEMCKE1-MEMCKE3 MEML(U)DQM Common to all waveforms shown above TMCLKH 0.8 DVDD 0.2 DVDD TMCSD TMCASD TMRASD TMWED TMCKED TMDQMD TMCSD TMCASD TMRASD TMWED TMCKED TMDQMD MEMD [31 : 0] MEMA [14 : 0] Common to all waveforms shown above TMAD TMDD 0.8 DVDD 0.2 DVDD TMAD TMDD Fig. 3 SDRAM Output Timing 0.8 DVDD MEMCLK (NOTE) 0.2 DVDD 0.8 DVDD MEMD [31 : 0] 0.2 DVDD TMDS TMDH Fig. 4 SDRAM Input Timing NOTE : MEMCLK is also used as the data latch clock inside the LR38666Y. Check the waveform of the incoming MEMCLK signal for no distortion. 16 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, C24MI = 24.5454 MHz, TA = 0 to +70C) PARAMETER Clock cycle Pulse width (High) Pulse width (Low) Chip select delay MEMRASZ output delay MEMCASZ output delay Write enable delay Addressing delay MEMCKE1 to MEMCKE3 output delay MEML(U)DQM output delay Data output delay (write cycle) Data setup delay (read cycle) Data hold delay (read cycle) SYMBOL TMCLK TMCLKH TMCLKL TMCSD TMRASD TMCASD TMWED TMAD TMCKED TMDQMD TMDD TMDS TMDH CONDITIONS MIN. 20 9 9 0 0 0 0 0 0 0 0 10 3 7 7 7 7 7 7 7 7 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns NOTE 2 2 2 1 2 2 2 2 1 2 2 NOTES : 1. Output load capacity CL = 10 pF 2. Output load capacity CL = 50 pF 17 LR38666Y FLASH MEMORY INTERFACE TIMING * Read/write timing READ cycle TMAS MEMA [20 : 0] TFOEHH TFOCELH TMAH FLCE0Z-FLCE1Z TMCC FL_EXWEZ TFLOEW TMDIS MEMD [15 : 0] Valid TMDIH FL_EXOEZ WRITE cycle TMAS MEMA [20 : 0] TFWEHH TFWCELH FWCELH TMAH FLCE0Z-FLCE1Z TMCC FL_EXWEZ TFLWEW FL_EXOEZ TMDOA MEMD [15 : 0] Valid TMDOH Fig. 5 Flash Memory Read/Write Cycle 18 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Address output setup time (relative to the falling edge of FLCE0Z/1Z) Address output hold time (relative to the rising edge of FLCE0Z/1Z) Minimum "High" period of FLCE0Z/1Z "High" hold time of FL_EXOEZ (relative to the falling edge of FLCE0Z/1Z) "Low" pulse width of FL_EXOEZ "Low" hold time of FLCE0Z/1Z (relative to the rising edge of FL_EXOEZ) "High" hold time of FL_EXWEZ (relative to the falling edge of FLCE0Z/1Z) "Low" pulse width of FL_EXWEZ "Low" hold time of FLCE0Z/1Z (relative to the rising edge of FL_EXWEZ) MEMD input setup time (relative to the rising edge of FL_EXOEZ) MEMD input hold time (relative to the rising edge of FL_EXOEZ) MEMD output delay (relative to the point at which the status of MEMA changes) MEMD output hold time (relative to the rising edge of FLCE0Z/1Z) SYMBOL TMAS TMAH TMCC TFOEHH TFLOEW CONDITIONS MIN. TCNT0 - 5 TCNT5 - 5 TCNT4 - 5 TCNT9 - 5 TCNT1 - 5 TCNT1 + 5 TCNT2 - 5 TCNT2 + 5 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 NOTE 2 2 1 2 2 1 2 2 1 TFOCELH TCNT3 - 5 TCNT3 + 5 TFWEHH TFLWEW TCNT6 - 5 TCNT6 + 5 TCNT7 - 5 TCNT7 + 5 TFWCELH TCNT8 - 5 TCNT8 + 5 TMDIS TMDIH TMDOA TMDOH 2TMCLK - 5 0 2TMCLK - 5 2TMCLK + 5 TCNT9 + TCNT9 + 2TMCLK - 5 2TMCLK + 5 NOTES : 1. Output load capacity CL = 15 pF 2. Output load capacity CL = 50 pF TCNT0, TCNT1, TCNT2, TCNT3, TCNT4, TCNT5, TCNT6, TCNT7, TCNT8, TCNT9 and each has a value within the following range depending on the register setting. TMAS corresponds to TCNT0 in read cycle and TCNT5 in write cycle, TMAH corresponds to TCNT4 in read cycle and TCNT9 in write cycle. TCNT0 : 1TMCLK to 3TMCLK, TCNT1 : 0TMCLK to 7TMCLK, TCNT2 : 3TMCLK to 15TMCLK, TCNT3 : 0TMCLK to 3TMCLK, TCNT4 : 1TMCLK to 3TMCLK, TCNT5 : 1TMCLK to 3TMCLK, TCNT6 : 0TMCLK to 7TMCLK, TCNT7 : 3TMCLK to 15TMCLK, TCNT8 : 0TMCLK to 3TMCLK, TCNT9 : 1TMCLK to 3TMCLK : Min. "High" period between read cycles : 3TMCLK (TCNT0 + TCNT4 + 1TMCLK) 7TMCLK Min. "High" period from read cycle to write cycle : 3TMCLK (TCNT4 + TCNT5 + 1TMCLK) 7TMCLK Min. "High" period from write cycle to read cycle : 3TMCLK (TCNT0 + TCNT9 + 1TMCLK) 7TMCLK Min. "High" period between write cycles : 3TMCLK (TCNT5 + TCNT9 + 1TMCLK) 7TMCLK 19 LR38666Y * Flash memory hard reset timing RESETZ TRPL FLRP0Z/1Z TRPH Fig. 6 Flash Memory Reset Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER "Low" pulse period of FLRP0Z/1Z (relative to the rising edge of RESETZ) "High" pulse period of FLRP0Z/1Z (relative to the rising edge of FLR0/1Z) SYMBOL TRPL TRPH CONDITIONS MIN. MAX. 11TMCLK 98TMCLK 12TMCLK UNIT ns ns NOTE 1 1, 2 NOTES : 1. Output load capacity CL = 15 pF 2. When the internal bus of the LR38666Y accesses to the flash memory during TRPH, it is made to wait. * Flash memory initialization timing TRPL FLRP0Z/1Z Fig. 7 Flash Memory Initialization Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER "Low" pulse period of FLRP0Z/1Z SYMBOL TRPL CONDITIONS MIN. 12TMCLK MAX. 12TMCLK UNIT ns NOTE 1 NOTE : 1. Output load capacity CL = 15 pF 20 LR38666Y INTERFACE TIMING OF OTHER DEVICES * S-type device timing READ cycle TMAS MEMA [20 : 0] TEOEHH TEOCSLH EOCSLH TMAH EXCS0Z-EXCS1Z TMCC FL_EXWEZ TEXOEW TMDIS MEMD [31 : 0] Valid TMDIH FL_EXOEZ WRITE cycle TMAS MEMA [20 : 0] TEWEHH TEWCSLH EWCSLH TMAH EXCS0Z-EXCS1Z TMCC FL_EXWEZ TEXWEW FL_EXOEZ TMDOA MEMD [31 : 0] Valid TMDOH Fig. 8 S-type Device Read/Write Cycle 21 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = -10 to +70C) PARAMETER Output setup period of MEMA (relative to the falling edge of EXCS0Z/1Z) Output hold period of MEMA (relative to the rising edge of EXCS0Z/1Z) Minimum "High" period of EXCS0Z/1Z "High" hold period of FL_EXOEZ (relative to the falling edge of EXCS0Z/1Z) "Low" pulse width of FL_EXOEZ "Low" hold period of EXCS0Z/1Z (relative to the rising edge of FL_EXOEZ) "High" hold period of FL_EXWEZ (relative to the falling edge of EXCS0Z/1Z) "Low" pulse width of FL_EXWEZ "Low" hold period of EXCS0Z/1Z (relative to the rising edge of FL_EXWEZ) Input setup period of MEMD (relative to the rising edge of FL_EXOEZ) Input hold period of MEMD (relative to the rising edge of FL_EXOEZ) Output delay period of MEMD (relative to MEMA) Output hold period of MEMD (relative to the rising edge of EXCS0Z/1Z) SYMBOL TMAS TMAH TMCC TEOEHH TEXOEW CONDITIONS MIN. TCNT00 - 5 TCNT05 - 5 TCNT04 - 5 TCNT09 - 5 TCNT01 - 5 TCNT01 + 5 TCNT02 - 5 TCNT02 + 5 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 NOTE 2 2 1 2 2 1 2 2 1 TEWCSLH TCNT03 - 5 TCNT03 + 5 TEWEHH TEXWEW TCNT06 - 5 TCNT06 + 5 TCNT07 - 5 TCNT07 + 5 TEWCSLH TCNT08 - 5 TCNT08 + 5 TMDIS TMDIH TMDOA TMDOH 2TMCLK - 5 0 2TMCLK - 5 2TMCLK + 5 TCNT09 + TCNT09 + 2TMCLK - 5 2TMCLK + 5 NOTES : 1. Output load capacity CL = 15 pF 2. Output load capacity CL = 50 pF TCNT00, TCNT01, TCNT02, TCNT03, TCNT04, TCNT05, TCNT06, TCNT07, TCNT08, TCNT09 and each has a value within the following range depending on the register setting. TMAS corresponds to TCNT00 in read cycle and TCNT05 in write cycle, and TCNT04 in read cycle and TCNT09 in write cycle. TCNT00 : 1TMCLK to 3TMCLK, TCNT01 : 0TMCLK to 3TMCLK, TCNT02 : 3TMCLK to 15TMCLK, TCNT03 : 0TMCLK to 7TMCLK, TCNT04 : 1TMCLK to 7TMCLK, TCNT05 : 1TMCLK to 3TMCLK, TCNT06 : 0TMCLK to 3TMCLK, TCNT07 : 3TMCLK to 15TMCLK, TCNT08 : 0TMCLK to 7TMCLK, TCNT09 : 1TMCLK to 7TMCLK : Min. "High" period between read cycles : 3TMCLK (TCNT00 + TCNT04 + 1TMCLK) 11TMCLK Min. "High" period from read cycle to write cycle : 3TMCLK (TCNT04 + TCNT05 + 1TMCLK) 11TMCLK Min. "High" period from write cycle to read cycle : 3TMCLK (TCNT00 + TCNT09 + 1TMCLK) 11TMCLK Min. "High" period between write cycles : 3TMCLK (TCNT05 + TCNT09 + 1TMCLK) 11TMCLK 22 LR38666Y * I-type timing READ cycle TMAS MEMA [20 : 0] TEOEHH TEOCSL TMAH EXCS0Z-EXCS1Z TMCC FL_EXWEZ FL_EXOEZ TMDIS MEMD [31 : 0] EXDACK0ZEXDACK1Z WRITE cycle TMAS MEMA [20 : 0] TEWEHH TEWCSLH EWCSLH TMAH TMDIS TMCACK Valid TMACKC TMACKH MACKH TMDIH MDIH EXCS0Z-EXCS1Z TMCC FL_EXWEZ FL_EXOEZ TMDOA MEMD [31 : 0] EXDACK0ZEXDACK1Z Valid TMACKH MACKH TMDOH TMACKC TMCACK Fig. 9 I-type Read/Write Cycle NOTE : It is able to invert the polarity of EXDACK0Z/1Z by internal register. 23 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = -10 to +70C) PARAMETER Output setup period of MEMA (relative to the falling edge of EXCS0Z/1Z) Output hold period of MEMA (relative to the rising edge of EXCS0Z/1Z) Minimum "High" period of EXCS0Z/1Z "High" hold period of FL_EXOEZ (relative to the falling edge of EXCS0Z/1Z) "Low" hold period of EXCS0Z/1Z (relative to the rising edge of FL_EXOEZ) "High" hold period of FL_EXWEZ (relative to the falling edge of EXCS0Z/1Z) "Low" hold period of EXCS0Z/1Z (relative to the rising edge of FL_EXWEZ) Input setup period of MEMD (relative to the falling edge of EXDACK0Z/1Z) Input hold period of MEMD (relative to the rising edge of FL_EXOEZ) Output delay period of MEMD (relative to MEMA) Output hold period of MEMD (relative to the rising edge of EXCS0Z/1Z) Setup period of EXDACK0Z/1Z (relative to the falling edge of FL_EXOEZ, FL_EXWEZ) Rising period of FL_EXOEZ/FL_EXWEZ (relative to the falling edge of EXDACK0Z/1Z) Hold period of EXDACK0Z/1Z (relative to the rising edge of EXCS0Z/1Z) SYMBOL TMAS TMAH TMCC TEOEHH CONDITIONS MIN. MAX. TCNT10 - 5 TCNT14 - 5 TCNT13 - 5 TCNT17 - 5 TCNT11 - 5 TCNT11 + 5 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 2 NOTE 2 2 1 2 1 2 1 TEOCSLH TCNT12 - 5 TCNT12 + 5 TEWEHH TCNT15 - 5 TCNT15 + 5 TEWCSLH TCNT16 - 5 TCNT16 + 5 TMDIS TMDIH TMDOA TMDOH TMCACK TMACKC TMACKH 0 0 2TMCLK - 5 2TMCLK + 5 TCNT17 + TCNT17 + 2TMCLK - 5 2TMCLK + 5 0 2TMCLK - 5 3TMCLK + 5 0 NOTES : 1. Output load capacity CL = 15 pF 2. Output load capacity CL = 50 pF TCNT10, TCNT11, TCNT12, TCNT13, TCNT14, TCNT15, TCNT16, TCNT17, and each has a value within the following range depending on the register setting. TMAS corresponds to TCNT10 in read cycle and TCNT14 in write cycle. TMAH corresponds to TCNT13 in read cycle and TCNT17 in write cycle. TCNT10 : 1TMCLK to 3TMCLK, TCNT11 : 0TMCLK to 3TMCLK, TCNT12 : 0TMCLK to 3TMCLK, TCNT13 : 1TMCLK to 3TMCLK, TCNT14 : 1TMCLK to 3TMCLK, TCNT15 : 0TMCLK to 3TMCLK, TCNT16 : 0TMCLK to 3TMCLK, TCNT17 : 1TMCLK to 3TMCLK : Min. "High" period between read cycles : 3TMCLK (TCNT10 + TCNT13 + 1TMCLK) 7TMCLK Min. "High" period from read cycle to write cycle : 3TMCLK (TCNT13 + TCNT14 + 1TMCLK) 7TMCLK Min. "High" period from write cycle to read cycle : 3TMCLK (TCNT10 + TCNT17 + 1TMCLK) 7TMCLK Min. "High" period between write cycles : 3TMCLK (TCNT14 + TCNT17 + 1TMCLK) 7TMCLK 24 LR38666Y * M-type timing READ cycle TMAS MEMA [20 : 0] TMAH EXCS0Z-EXCS1Z TMCC FL_EXWEZ TMDIS MEMD [31 : 0] EXDACK0ZEXDACK1Z TMCACK Valid TMACKC TMACKH TMDIH WRITE cycle TMAS MEMA [20 : 0] TMCC TMAH EXCS0Z-EXCS1Z FL_EXWEZ TMDOA MEMD [31 : 0] EXDACK0ZEXDACK1Z TMCACK TMACKC Valid TMACKH MACKH TMDOH Fig. 10 M-type Read/Write Cycle NOTE : It is able to invert the polarity of EXDACK0Z/1Z by internal register. 25 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Output setup period of MEMA (relative to the falling edge of EXCS0Z/1Z) Output hold period of MEMA (relative to the rising edge of EXCS0Z/1Z) Minimum "High" period of EXCS0Z/1Z Input setup period of MEMD (relative to the falling edge of EXDACKZ) Input hold period of MEMD (relative to the rising edge of EXCS0Z/1Z) Output delay period of MEMD (relative to MEMA) Output hold period of MEMD (relative to the rising edge of EXCS0Z/1Z) Setup period of EXDACK0Z/1Z (relative to the falling edge of EXCS0Z/1Z) Rising period of EXCS0Z/1Z (relative to the falling edge of EXDACK0Z/1Z) Hold period of EXDACK0Z/1Z (relative to the rising edge of EXCS0Z/1Z) SYMBOL TMAS TMAH TMCC TMDIS TMDIH TMDOA TMDOH TMCACK TMACKC TMACKH CONDITIONS MIN. TCNT20 - 5 TCNT22 - 5 TCNT21 - 5 TCNT23 - 5 0 0 2TMCLK - 5 2TMCLK + 5 TCNT23 + TCNT23 + 2TMCLK - 5 2TMCLK + 5 0 2TMCLK - 5 3TMCLK + 5 0 MAX. UNIT ns ns ns ns ns ns ns ns ns ns 1 2 2 NOTE 2 2 1 NOTES : 1. Output load capacity CL = 15 pF 2. Output load capacity CL = 50 pF TCNT20, TCNT21, TCNT22, TCNT23, and each has a value within the following range depending on the register setting. TMAS corresponds to TCNT20 in read cycle and TCNT22 in write cycle, and TMAH corresponds to TCNT21 in read cycle and TCNT23 in write cycle. TCNT20 : 1TMCLK to 3TMCLK, TCNT21 : 1TMCLK to 3TMCLK, TCNT22 : 1TMCLK to 3TMCLK, TCNT23 : 1TMCLK to 3TMCLK : Min. "High" period between read cycles : 3TMCLK (TCNT20 + TCNT21 + 1TMCLK) 7TMCLK Min. "High" period from read cycle to write cycle : 3TMCLK (TCNT21 + TCNT22 + 1TMCLK) 7TMCLK Min. "High" period from write cycle to read cycle : 3TMCLK (TCNT20 + TCNT23 + 1TMCLK) 7TMCLK Min. "High" period between write cycles : 3TMCLK (TCNT22 + TCNT23 + 1TMCLK) 7TMCLK 26 LR38666Y * CompactFlash attribute memory access timing READ cycle TMASR CFREGZ MEMA [20 : 15] & CFA [4 : 0] TMCC TMAHR CFCE1Z-CFCE2Z FL_EXWEZ TCFOEW TMDIS CFD [15 : 0] Valid TMDIH FL_EXOEZ WRITE cycle TMASW CFREGZ MEMA [20 : 15] & CFA [4 : 0] TCWEHH TCWCSLH CWCSLH TMCC TMAHW CFCE1Z-CFCE2Z FL_EXWEZ TCFWEW FL_EXOEZ TMDOA CFD [15 : 0] Valid TMDOH Fig. 11 CompactFlash Attribute Memory Read/Write Cycle 27 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Output setup period of MEMA [20 : 15] & CFA at reading (relative to the falling edge of CFCE1Z/2Z) Output setup period of MEMA [20 : 15] & CFA at writing (relative to the falling edge of CFCE1Z/2Z) Output hold period of MEMA [20 : 15] & CFA at reading (relative to the rising edge of CFCE1Z/2Z) Output hold period of MEMA [20 : 15] & CFA at writing (relative to the rising edge of CFCE1Z/2Z) Minimum "High" period of CFCE1Z/2Z "Low" pulse width of FL_EXOEZ "High" hold period of FL_EXWEZ (relative to the falling edge of CFCE1Z/2Z) "Low" pulse width of FL_EXWEZ "Low" hold period of CFCE1Z/2Z (relative to the rising edge of FL_EXWEZ) Input setup period of CFD (relative to the rising edge of FL_EXOEZ) Input hold period of CFD (relative to the rising edge of FL_EXOEZ) Output delay period of CFD (relative to MEMA [20 : 15] & CFA) Output hold period of CFD (relative to the rising edge of FL_EXWEZ) SYMBOL TMASR TMASW TMAHR TMAHW TMCC TCFOEW CONDITIONS MIN. 2TMCLK - 5 TMCLK - 5 3TMCLK - 5 TMCLK - 5 3TMCLK - 5 17TMCLK - 5 17TMCLK + 5 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 NOTE 2 2 2 2 1 1 1 1 1 TCWEHH 2TMCLK - 5 2TMCLK + 5 TCFWEW 8TMCLK - 5 8TMCLK + 5 TCWCSLH 2TMCLK - 5 2TMCLK + 5 TMDIS TMDIH TMDOA TMDOH 2TMCLK - 5 0 2TMCLK - 5 2TMCLK + 5 5TMCLK - 5 5TMCLK + 5 NOTES : 1. Output load capacity CL = 50 pF 2. MEMA [20 : 15] output load capacity CL = 50 pF, CFA [4 : 0] output load capacity CL = 30 pF. 28 LR38666Y * CompactFlash common memory access timing READ cycle TMASR CFREGZ MEMA [20 : 15] & CFA [4 : 0] TEOEHH TEOCSL TMCC TMAHR CFCE1Z-CFCE2Z FL_EXWEZ FL_EXOEZ TMDIS CFD [15 : 0] Valid TMDIH CFWAITZ TMCACK TMACKCR TMACKH WRITE cycle TMASW CFREGZ MEMA [20 : 15] & CFA [4 : 0] TEWEHH CFCE1Z-CFCE2Z TEWCSLH EWCSLH TMCC TMAHW FL_EXWEZ FL_EXOEZ TMDOA CFD [15 : 0] Valid TMCACK TMACKCW TMACKH TMDOH CFWAITZ Fig. 12 CompactFlash Common Memory Read/Write Cycle 29 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Output setup period of MEMA [20 : 15] & CFA at reading (relative to the falling edge of CFCE1Z/2Z) Output setup period of MEMA [20 : 15] & CFA at writing (relative to the falling edge of CFCE1Z/2Z) Output hold period of MEMA [20 : 15] & CFA at reading (relative to the rising edge of CFCE1Z/2Z) Output hold period of MEMA [20 : 15] & CFA at writing (relative to the rising edge of CFCE1Z/2Z) Minimum "High" period of CFCE1Z/2Z "High" hold period of FL_EXOEZ (relative to the falling edge of CFCE1Z/2Z) "Low" hold period of CFCE1Z/2Z (relative to the rising edge of FL_EXOEZ) "High" hold period of FL_EXWEZ (relative to the falling edge of CFCE1Z/2Z) "Low" hold period of CFCE1Z/2Z (relative to the rising edge of FL_EXWEZ) Input setup period of CFD (relative to the rising edge of CFWAITZ) Input hold period of CFD (relative to the rising edge of FL_EXOEZ) Output delay period of CFD (relative to MEMA [20 : 15] & CFA) Output hold period of CFD (relative to the rising edge of CFCE1Z/2Z) Determination period of CFWAITZ (relative to the falling edge of FL_EXOEZ/FL_EXWEZ) Rising period of FL_EXOEZ (relative to the rising edge of CFWAITZ) Rising period of FL_EXWEZ (relative to the rising edge of CFWAITZ) Hold period of CFWAITZ (relative to the rising edge of EXDACK0Z/1Z) SYMBOL TMASR TMASW TMAHR TMAHW TMCC TEOEHH CONDITIONS MIN. TMCLK - 5 TMCLK - 5 2TMCLK - 5 TMCLK - 5 3TMCLK - 5 TMCLK - 5 TMCLK + 5 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 NOTE 2 2 2 2 1 1 1 1 1 TEOCSLH 2TMCLK - 5 2TMCLK + 5 TEWEHH TMCLK - 5 TMCLK + 5 TEWCSLH 2TMCLK - 5 2TMCLK + 5 TMDIS TMDIH TMDOA TMDOH TMCACK 0 0 2TMCLK - 5 2TMCLK + 5 5TMCLK - 5 5TMCLK + 5 2TMCLK + 5 TMACKCR 2TMCLK - 5 3TMCLK + 5 TMACKCW 4TMCLK - 5 5TMCLK + 5 TMACKH 0 NOTES : 1. Output load capacity CL = 50 pF 2. MEMA [20 : 15] output load capacity CL = 50 pF, CFA [4 : 0] output load capacity CL = 30 pF. 30 LR38666Y * SmartMedia access timing READ cycle TMASR CFA4 (as CLE) TMAHR CFA3 (as ALE) CFRST (as -CE) CFA1 (as -WE) TSOEHH CFA0 (as -RE) TSMOEW TMDIS CFD [7 : 0] Valid TMDIH Valid WRITE cycle TMASW CFA4 (as CLE) TMAHW CFA3 (as ALE) CFRST (as -CE) CFA1 (as -WE) TSMWEW TSWEHH CFA0 (as -RE) TMDOA CFD [7 : 0] Valid TMDOH Valid TMDOH Fig. 13 SmartMedia Read/Write Cycle 31 LR38666Y (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Output setup period of CLE, ALE, -WE at reading (relative to the falling edge of -RE) Output setup period of CLE, ALE, -RE at writing (relative to the falling edge of -WE) Output hold period of CLE, ALE, -WE at reading (relative to the rising edge of -RE) Output hold period of CLE, ALE, -RE at writing (relative to the rising edge of -WE) "Low" pulse width of -RE "High" pulse width of -RE "Low" pulse width of -WE "High" pulse width of -WE Input setup period of CFD [7 : 0] (relative to the rising edge of -RE) Input hold period of CFD [7 : 0] (relative to the rising edge of -RE) Output delay period of CFD [7 : 0] (relative to the rising edge of CLE, ALE) Output hold period of CFD [7 : 0] (relative to the rising edge of -WE) SYMBOL TMASR TMASW TMAHR TMAHW CONDITIONS MIN. 2TMCLK - 5 2TMCLK - 5 3TMCLK - 5 3TMCLK - 5 MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns 1 1 NOTE 1 1 1 1 1 1 1 TSMOEW 4TMCLK - 5 4TMCLK + 5 TSOEHH 2TMCLK - 5 2TMCLK + 5 TSMWEW 3TMCLK - 5 3TMCLK + 5 TSWEHH TMDIS TMDIH TMDOA TMDOH 2TMCLK - 5 2TMCLK + 5 2TMCLK - 5 0 2TMCLK - 5 2TMCLK + 5 2TMCLK - 5 2TMCLK + 5 NOTE : 1. Output load capacity CL = 50 pF 32 LR38666Y USB TIMING * USB transmitting timing TWPUT TWPUT GIO9 (as TX_VPO) GIO10 (as TX_VMO) TWPUT GIO11 (as TX_OE_N) TOED GIO12 (as SUSPEND_N) Fig. 14 USB Transmitting Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Transmission period of 1 bit Output delay period of TX_OE_N SYMBOL TWPUT TOED CONDITIONS MIN. 80 162 TYP. 83 167 MAX. 86 172 UNIT ns ns NOTE 1, 2 2 NOTES : 1. When "High" or "Low" continues for N bits period, it is (48 MHz)-1 x 4 x N3 ns. 2. Output load capacity CL = 15 pF 3. USB module will be reset when SE0 status (GIO13 = GIO14 = "Low") is input longer than 2.5 s, in transmitting, so choose USB transceiver IC carefully. 33 LR38666Y * USB receiving timing TWPUR TWPUR GIO13 (as RX_VPI) GIO14 (as RX_VMI) GIO15 (as RX_DATA) TWPUR TDRCV Fig. 15 USB Receiving Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Receiving period of 1 bit Permissible delay period of received data SYMBOL TWPUR TDRCV CONDITIONS MIN. 68 0 TYP. 83 MAX. 98 14 UNIT ns ns NOTE 1 NOTE : 1. When "High" or "Low" continues for N bits period, it is (48 MHz)-1 x 4 x N3 ns. UART TIMING TWPAR SDI1 TWPAT SDO1 Fig. 16 UART Communication Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER SDI1 input pulse width SDO1 output pulse width SYMBOL TWPAR TWPAT CONDITIONS MIN. 8.57 8.57 TYP. MAX. UNIT s s NOTE 2 1, 2 NOTES : 1. Output load capacity CL = 15 pF 2. The baud rate is assumed to be 115.2 k bps. 34 LR38666Y USART TIMING TSCLKI SCLKI TSDI0S TSDI0H SDI0 TSCLKO SCLKO TSDO0D SDO0 Fig. 17 USART Communication Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER SCLKI clock input cycle SDI0 input setup time SDI0 input hold time SCLKO clock output cycle SDO0 output delay SYMBOL TSCLKI TSDI0S TSDI0H TSCLKO TSDO0D CONDITIONS TYP. MAX. TBRCK 1/4 TBRCK 1/4 TBRCK TBRCK -1/4 TBRCK 1/4 TBRCK MIN. UNIT ns ns ns ns ns NOTE 2 2 2 1, 2 1, 2 NOTES : 1. Output load capacity CL = 15 pF 2. TBRCK means the baud rate clock frequency. If COMI (24 MHz) is used and baud rate generator control register BKGC is set to 0x138 (9 600 bps), TBRCK is given as follows : TBRCK = [48 MHz/(312*16)]-1 = 104 s GIO PORT PWM OUTPUT TIMING TPWML GIO [15 : 0] TPWMW TPWMH Fig. 18 GIO I/O Timing PARAMETER Output pulse width "Low" output pulse width "High" output pulse width SYMBOL TPWMW TPWML TPWMH CONDITIONS 256 0 to 256 TPWMW - TPWML UNIT TBCLK TBCLK TBCLK NOTE 1, 2 1, 2 1, 2 NOTES : 1. Output load capacity CL = 15 pF 2. TBCLK is twice the internal bus clock period. 35 LR38666Y CCD INTERFACE TIMING TGCLK THDD HD TVDD VD TCCDGED GIO (as CCDGEO) TCCDIS CCDIN [9 : 0] TCCDIH Fig. 19 CCD Data Input Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER HD output delay VD output delay CCDGEO output delay CCDIN input setup time CCDIN input hold time SYMBOL THDD TVDD TCCDGED TCCDIS TCCDIH 10 10 CONDITIONS MIN. TYP. MAX. 15 15 15 UNIT ns ns ns ns ns NOTE 1 1 1 NOTE : 1. Output load capacity CL = 15 pF 36 LR38666Y AUDIOIF TIMING TASCLK ASCLK TASDIS TASDIH ASDI TASDOD ASDO TARSYNCOD ARSYNCO TAXSYNCOD AXSYNCO TASCLK ASCLK TASDIS TASDIH ASDI TASDOD ASDO TARSYNCOD ARSYNCO TAXSYNCOD AXSYNCO Fig. 20 AUDIOIF Communication Cycle (DVDD = 3.3 V, DVDD2 = 2.5 V, TA = 0 to +70C) PARAMETER Input setup period of ASDI Input hold period of ASDI Clock output cycle of ASCLK Output delay period of ASDO Output delay period of ARSYNCO Output delay period of AXSYNCO CONDITIONS MIN. TYP. MAX. TASDIS 1/4 TASCK TASDIH 1/4 TASCK TASCLK TASCK TASDOD 20 TARSYNCOD 20 TAXSYNCOD 20 SYMBOL UNIT ns ns ns ns ns ns NOTE 2 2 1, 2 1 1 1 NOTES : 1. Output load capacity CL = 15 pF 2. TASCK means the clock period of bit-shift-clock. If the sampling clock frequency is 32 kHz, TCLK input is 16.384 MHz (512 fs) and bit-shift-clock register (BSCG) is set to 0x0010 (bit-shift-clock is 1.024 MHz or 32 fs), TASCK is given as follows : TASCK = (16.384 MHz/16)-1 = 976.5625 ns 37 LR38666Y PACKAGE OUTLINES 240 CSP (T-TFBGA240-1414) (Unit : mm) A B Index S 0.15 S 0.15 S 1.0TYP. 0.8TYP. 0.4TYP. ABCDEFGH J K LMNPR T D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0.4TYP. 0.8TYP. 1.0TYP. C 0.350.05 14.0+0.2 0 1.2MAX. O0.30 O0.15 14.0+0.2 0 M M S S AB CD O0.450.05 38 |
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